EASY WAY TO PASS CIT 292 AND CIT 246

         1.     Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48mhz 

(a)     10.24kmz

(b)    5khz

(c)      30.24hz

(d)     15khz                                                                                                                                                                                                                                 

           2.    Which statement best describe the operation of a negative edge-triggered D flip-flop?

(a)  The logic level at the D input is transferred to Q on NGT of CLK

(b)  The output is always identical to the CLK input if the D input is high

(c)   The Q output is always identical to the D input when CLK=PGT

(d)  The Q output is always identical to the D input

             3.    Propagation delays time,  tPLH is measured from the ……………..

        (a) Triggering edge of the clock pulse to the high transition of the output

          (b) Triggering edge of the clock pulse to the high to low transition of the output

           (c) Present input to the low to high transition of the output

           (d) Clear input to the high to low transition of the output

             4.    How is a j-k flip-flop made to toggle

          (a)J=0, K=0

          (b)J=1, K=0

          (c)J=0, K=0

          (d)J=1, K=1

             5.    How many flip-flop are in the 7475 1c

      (a) 1

      (b) 2

      (c) 4

       (d) 8

            6.    How many flip-flops are in the required to produce a divide-by-128 device

       (a) 1

       (b) 4

       (c) 6

       (d) 7

             7.    Which is not an altera primitive port identifier

        (a) clk

        (b) ena

         (c) clr

         (d) prn

              8.    The timing network that sets the output frequency of a 555 astable circuit contains

         (a) Three astable resistors and used

         (b) Two external resistors and two-external capacitors are used

         (c) An external resistors and two-external capacitors are used

         (d) No external resistor or capacitors is required

               9.    What is the difference b/w the enable inputs of the clock input of the 7474

(a)   The 7475 is edge triggered

(b) The 7474 is edge triggered

10.The phenomenon of interpreting unwanted signals on J and K while (clock pulse) is high is called ……………

            (a) Parity error checking

            (b) Ones catching

            (c) Digital discrimination

             (d) Digital filtering

11. What is another name for a one-shot

 (a)  Menostable

           (b) Multivibrator

           (c)  Bistable

              (d)   Astable

12. On a master-slave flip-flop when is the master enable.

·       When the gate is low

·       When the gate is High

·       Both of the above

·       Neither of the above

     13.One example of the use of an S-R flip-flop is a

·       Racer

·       Astable oscillator

·       Binary storage register

·       Transition pulse generator

14.What is the difference between the 7476 and the 74 & 576

·       The 7476 is master-slave, the 741576 is master slave

·       The 7476 is edge-triggered, the 741576 is edge-triggered

·       The 7474 is edge triggered,  the 741576 is master-slave

·       The 7474 is master-slave, the 741576 is-slave, the 741576 is edge-triggered

15.With regard to a D catch, …………………..

·       The Q output follows the D input when EN is low

·       The Q output is opposite the D input when EN is low

·       The Q output follows the D input when EN is High

·       The Q output flow is High regardless of SN’s input state

16. How can the cross-coupled NAND flip-flop be made to have active-high S-R inputs.

·       It can’t be done

·       Invert the Q outputs

·       Invert the S-R inputs

17.When is a flip-flop said to be transparent.

·       When the Q output is opposite the input

·       When the Q output follows the input

·       When you can see through the IC packaging

·       When the Q input follows the output

18.A 555 operating as a monostable multivibrator has R, of 1Mn Determine C for a pulse width of 25.

·       1.8 uf

·       18f

·       18gf

·       18nf

19.Master-slave J-X flips are called pulse triggered or level-triggered devices be clock pulse is at low level.

·       True

·       False

20.Which of the following is correct for D catch

·       The output toggles if one of the inputs is held high

·       Q outputs follows the input D when the enable is high

·       Only one of the inputs can be High at a time

·       The output complement follows the input when enabled

21.A J-K flip-flop is in a “nochange” condition when ……………

·       J=1, K=1

·       J=1, K=0

·       J=0, K=1

·       J=0, K=0

22.A correct output is achieved from a master slave J.K flip-flop only if input are stable while the…………..

·       Clock is low

·       Slave is transforming

·       Flip-flop is reset

·       Clock is High

23.Which of the following describes the operation of a positive edge-triggered D flip-flop.

·       If both inputs are high , the output will toggle.

·       The output will follow the input on the leading edge of the clock

·       When both inputs are low,an invalid state exists.

·       The input is toggled into the flip-flop on the leading edge of the trailing edge of the clock.

24. What does the triangle on the clock input of a J-k flip-flop mean

·       Level enabled

·       Edge triggered

25.A J-k flip-flops with J=1 and K=1 has a 20khz input. The output is ……………..

·       Constantly

·       Constantly high

·       A 10khz square wave

26.The toggle condition in a master-slave J-K flip-flop means that Q and Q’ will switch to their state(s) at the ……………

·       Opposite, active clock edge

·       Inverted, positive clock edge

·       Quiescent, Negative clock edge

·       Reset, synchronous clock edge

27.An Rc circuit used in a non-retriggerable 74(2) one shot has an REXT of 49kv,and a CEXT of 0.2uf. The pulse width  (fw) is approximately ……………

·       6.9as

·       6.9ms

·       69ms

·       690ms

28.On a positive edge-triggered S-R flip-flop the outputs reflects the input condition when ……………

·       The clock pulse is low

·       The clock pulse is high

·       The Clock pulse transitions from low to high

·       The clock pulse transition from high to low

29.If an active high S-V catch a 0 on the S input and a 1 on the R input and when the R inputs goes to, the catch will be ……….

·       Set

·       Reset

·       Clear

·       Invalid

30.What is the hold condition of a flip-flop?

·       Both S and R inputs activated

·       No active S or R input

·       Only S is active

·       Only R is active

31.In VHDL, how many inputs will a primitive JK flip-flop have

·       2

·       3

·       4

·       5

32.A 555 operating as a monostable multivibrator has a                G =0.01uf Determine R, for a pulse width of 2ms

·       200n

·       182kn

·       91kn

·       182n

33.AD flip-flop utilizing a PGT clock is in the clear state, Which of the following input actions will cause it to change states

·       CLK = NGT, D = 0

·       CLK = PGT< D = 0

·       Clock NGT, D = 1

·       Clock PGT, D = 1

34. The symbol on this flip-flop device indicates

·       Triggering takes place on the negative-going edge of the CLK pulse.

·       Triggering takes place on the positive-going edge of the CLK pulse

·       Triggering can take place anytime during the high level of the CLK waveform

·       Triggering can take place anytime during the low level of the CLK waveform.

35. In a 555time, where 5k or resistors gravite a trigger level of ………..

·       ¼ Vcc and threshold level ½ Vcc

·       1/3 Vcc and a threshold level ¾ Vcc

·       1/3 Vcc and a threshold level 2/3 Vcc

·       ¼ Vcc and a threshold level ¾ Vcc

36.Does the cross-coupled NOR flip-flop have active-high or active-low and reset inputs.

·       Active-High

·       Active-low

·       Non of the above

·       All of the above 

37.The circuit that is primarily responsible for certain flip-flops to be designed as edge triggered is the …………..

·       Edge detection circuit

·       NOR catch

·       NAND catch

·       Pulse-steering circuit

38.With J-k flip-flop wired as a asynchronous counter, first output change of divider 4 indicates a count of how many input clock pulses.

·       16

·       8

·       4

·       2

39.What is the significance of the J and K terminals on the J-K flip-flop

·       There is no known significance in their designations

·       Output reacts whenever the clock goes high and the J input is also high.

·       The letters were chosen in honor of Jack kilby, the inventery of the integrated circuit.

·       All of the other letters of the alphabet are already in use.

40. Why are the S and R inputs of a gated flip-flop said to be signatronous.

·       They must occur with the gate

·       They occur independent of the gate

·       The inputs are applied after the gate pulse

·       None of the above.

41.Gated S-R flip-flop are called asynchronous because the output responds immediately to input changes

·       True

·       False

·       42. Which of the following is not generally associated with flip-flops.

·       Hold time

·       Propagation delay time

·       Interval time

·       Set up time

43. An RC Circuit used in a 74122 retriggerable one-shot has an REXT of 100kw and a CEXT of 0.005uf. The pulse width 13 ………………

·       70us

·       16us

·       160us

·       32us

44. Edge-triggered flip-flops must have

·       Very fast response times

·       At least two inputs to handle rising and falling edges.

·       Positives edge-detection circuits

·       Negative edge-detection circuits.

45. A 555 operating as a monostable multivibrator has an R , of 220kw. Determine C, for a pulse width of 4ms

·       17pf

·       17uf

·       170pf

·       1,700uf

46. What is one disadvantages of an S-R flip-flop.

·       It has no enable input

·       It has an invalid state

·       It has no clock input

·       It has only a single output.

47. To completely load and then unload an 8-bit register requires how many clock pulses.

·       2

·       4

·       8

·       16

48. What is one disadvantages of an sure flip-flop.

·       It has no enable

·       It has an invalid state

·       It has no clock input

·       It has a single output

49. Which of the following best describes the actions of pulse-triggered ff’s

·       The clock and the S-R inputs must pulse shaped.

·        The data is entered on the leading edge of the clock, and transferred out on the training edge of the clock.

·       A pulse on the clock transfers data from input to output.

·       The synchronous inputs must be pulsed.

50. An invalid condition in the operation of an active High inputs negative catch occurs when

·       Highs are applied simultaneously to both inputs S and R

·       Lows are applied to simultaneously to both inputs S and R

·       A low is applied to the S input while A high is applied to the R input

·       A high is applied to the S inputs while a low is applied to the R input

51. On a g-k flip-flop, when is the flip-flop in a hold condition

·       J = 0, K = 0

·       J = 1, K = 0

·       J = 1, K = 0

·       J = 0, K = 1

·       J = 1, K = 1

52. The output pulse width for a 555 monostable circuit with R=33kw and C1=02, is ………..

·       7.3us

·       73us

·       7,3mms

·       73ms

53. Edge-triggered flip-flops must have

·       Very fast response times

·       At least two inputs to handle rising and falling edges.

·       A pulse transition detector

·       Active-low inputs and complemented outputs.

54. As a general rule for stable flip-flop triggering the clock pulse rise and fall times must be.

·       Very long

·       Very short

·       All of the above

·       Non of the above

55. A positive edge-triggered D flip-flop will store a 1 when ……….

·       The D input is high and the clock transitions from high low  to high.

·       The D input is high and the clock transitions from low to high

·       The D input is high and the clock is low

·       The D input is high and the clock is high

56. If an input is activated by a signal transition, it is ………..

·       Edge-triggered

·       Toggle-triggered

·       Clock-triggered

·       Noise-triggered

57.A 555 operating as a monostable multivibrator has a C, =100NF, Determine R, for a pulse width of 500Ms.

·       45n

·       455n

·       4.5kn

·       455kn

58.Asynchronous inputs will cause the flip-flop to respond immediately with regard to the clock point.

·       True

·       False

59. Which is not a real advantages of VHDL?

·       Using high levels of abstraction.

·       Tailoring components to exactly fit the needs of project.

·       The use of graphical tools.

·       Using higher levels of abstraction and tailoring components to exactly fit the needs of project.

60.Two J-k flip-flops with their J-K inputs filled high are cascaded to be used as counters. After four input clock pulses, The binary count is …………..

·       00

·       11

·       01

·       10

61.Catches constructed with NOR AND NAND gates tend to remain in the catched condition due to which configuration feature?

·       Cross Coupling

·       Gate impedance

·       Low input voltages

·       Asynchronous operation

62. In VHDL, how is each instance of a components addressed?

·       A name followed by a colon and the name of the library primitive.

·       A name followed by a semi colon and the components type.

·       A name followed by the library being used.

·       A name followed by the components library number

63. The output of a gated S-R flip=flop changes only if the.

·       Flip-flop is set.

·       Control input data has changed.

·       Flip-flop is reset

·       Input data has no change.

64. In VHDL, in which delaration section is a COMPONENT declared?

·       Architecture

·       Library

·       Entity

·       Port map

65. The output pulse width of a 555 monostable circuit with R,=47kn and G=47nf is ………….

·       24sec

·       24ms

·       243ms

·       243us

66. If both inputs of an S-R flip-flop are low, what will happen when the clock goes High?

·       An invalid state will exit.

·       No change will occur in output.

·       The output will toggle

·       The output will reset

67. A push-button switch is used to input data to a register, the output of the register is erratic, what could be causing the problem?

·       The power supply is probably noisy.

·       The switch contacts are bouncing.

·       The socket contacts on the register IC are corroded

·       The register IC is intermittent and failure is imminent.

68. The pulse with of a one-shot circuit is determined by …….

·       A resistor and capacitor

·       Two resistors.

·       Two capacitors

·       None of the above

69. For an S-R flip-flop to be set or reset, respective input must be:

·       Installed with steering diodes.

·       In parallel with a limiting resistor

·       Low

·       High 

70. An active-high input S-R latch has 1 on the state the latch is in?

·       Q = 1, Q = 0

·       Q = 1, Q = 1

·       Q = ?, Q = 0

·       Q = ?, Q = 0s

71. If both inputs and outputs of an S-R flip-flop are low, what will happen when the clock goes high?

·       No change will occur in the output

·       An invalid state will exist

·       The output will toggle

·       The output will reset

72. Four J-K flip-flop are cascaded with their J-K inputs tied high. If the input frequency (f in) to the first flip-flop is 32KHZ,the output frequency (f out) is ____________

·       1KHZ

·       2KHZ

·       4KHZ

·       16KHZ

73. Preset and clear inputs are normally synchronous.

·       True

·       False

74. A negative edge triggered flip-flop will accept input only when the clock is low.

·       True

·       False

75.A gated S-R flip-flop goes into the set condition when S is High ; ie is  low, and EN is High.

·       True

·       False

76. VHDL does requires a special designation for an output with feedback.

·       True

·       False

            77. The term clear always means that’s Q = 0, Q = 1

·       True

·       False

78. The Q output of a flip-flop is normally High when the device is the “clear” or “reset” state

·       True

·       False

79. An astable multivation is sometimes reffered to as clock

·       True

·       False

80. Lager subcubes requires fewer _______ becomes of fewer variable in the product term

·       AND gates

·       OR gates

·       NOR gates

·       XOR gates